1. Field of the Invention
The present invention relates to a method for producing a thin film semiconductor device utilizing a polycrystalline silicon thin film. More particularly, the present invention relates to a method for producing a thin film semiconductor device such as a thin film transistor (hereinafter, simply referred to as a "TFT") that can be used as a switching element or in a peripheral driving circuit in a liquid crystal display (hereinafter, simply referred to as an "LCD").
2. Description of the Related Art
Recently, polycrystalline silicon thin film semiconductor devices utilizing polycrystalline silicon thin films as semiconductor layers, e.g., TFTs, are used in thin film transistor liquid crystal display devices (TFT-LCD devices), for example, as pixel transistors, or in peripheral driving circuits. However, such TFTs have a drawback in that a substantial amount of leakage current is generated during the OFF-period due to the material characteristics of the polycrystalline silicon thin film.
One of the major causes of such a leakage current is an avalanche current generated by an electric field concentration at the junctions of an intrinsic semiconductor region where it interfaces with impurity diffused regions (i.e., either the n.sup.+ regions or the p.sup.+ regions). Conventionally, in order to restrain such a phenomenon from occurring, an offset structure or an LDD (lightly doped drain) structure is formed.
Moreover, the polycrystalline silicon has a drawback in that it includes a great number of dangling bonds particularly in grain boundaries. Since these dangling bonds adversely affect the operating characteristics of the thin film semiconductor device as a transistor, it is necessary to embed ions such as hydrogen ions in the dangling bonds. This method is generally referred to as "hydrogenation".
Conventional hydrogenation of a polycrystalline silicon TFT is disclosed, for example, in the documents listed below. According to any one of these documents, the hydrogenation is performed after the formation of the impurity diffused regions (i.e., either the n.sup.+ regions or the p.sup.+ regions).
Japanese Patent Publication No. 6-1786 discloses a method in which hydrogen ions are implanted into an intrinsic semiconductor layer. In Japanese Patent Publication No. 3-57613, an intrinsic semiconductor layer is heated in a hydrogen atmosphere. In Japanese Patent Publication No. 62-45712, an intrinsic semiconductor layer is heated in a hydrogen plasma atmosphere. In Japanese Laid-Open Patent Publication No. 4-57098, a nitrogen silicon semiconductor layer is heated after forming a protection film of plasma nitrogen silicon.
Impurities such as phosphorus or boron are contained as dopants in a polycrystalline silicon film in order to form contact regions (i.e., either the n.sup.+ regions or the p.sup.+ regions) of a polycrystalline silicon TFT using a method that does not cause mass separation (e.g., an ion shower doping method or an ion implantation method). However, in such methods, the introduced impurities undesirably diffuse in a lateral direction toward a channel region in a subsequent heating process. Particularly, unlike in the case of single crystalline silicon, polycrystalline silicon includes grain boundaries along which the diffusion speed of the impurities is significantly faster compared with that inside the grains. Therefore, due to the lateral diffusion of the impurities toward the channel region, an effective offset length or LDD length may be undesirably shortened in the order of micrometers in the polycrystalline silicon TFTs.
Particularly, in the above-described conventional hydrogenation method, heat treatment for hydrogenation is conducted after forming the contact regions (either the n.sup.+ regions or the p.sup.+ regions), i.e., after introducing the impurities. Hence, the above-described lateral diffusion of the impurities, which causes an undesirable decrease in the offset length or the LDD length, is more likely to occur. As a result, the initial offset length or the initial LDD length must be set to such a value that allows for its expected decrease. However, setting the initial offset length or the initial LDD length to such a value prevents the size reduction of the TFT.
Moreover, a polycrystalline silicon TFT has a higher interface level concentration between a gate insulating film and the intrinsic semiconductor region compared with that of a single crystalline silicon TFT. Therefore, the impurities introduced in the contact regions (the n.sup.+ regions or the p.sup.+ regions) are more likely to undesirably diffuse in the lateral direction along the interface between the gate insulating film and the intrinsic semiconductor region. Therefore, when the channel length of the TFT is set to several micrometers or less for realizing the size reduction of the TFT, the gate voltage-drain current characteristic curve undesirably shifts. Specifically, in the case of an n-channel, the curve shifts in the negative direction; and in the case of a p-channel, the curve shifts in the positive direction.
Because of the above-described mechanisms, the conventional heat treatment for the hydrogenation, which is conducted after the formation of the contact regions, i.e., after the doping of the impurities, promotes undesirable diffusion of the impurities in the lateral direction. As a result, there is a limit in the shortening of the channel length and thus the size reduction of the TFT is also limited.